A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Friday, June 22, 2012
Frustrations
I am running into many snags now, with the alu and control module. It's slowing me down but I'm certain I can get it up and running in no time. Also, the deadline for the progress report is fast approaching so it's time for my least favorite task.
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