A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Tuesday, June 5, 2012
Software registers
<p>Preliminary tests on the sw regs are promising. 64 of them ought to be <br>
plenty. Still reasoning out how to use an sfr to control the gpios but lots of time for that.
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