Presentation Day

I hope Steve likes what I've accomplished with this processor. I'm sure proud it. There's lots more I can do, but I did what I set out to do and produced something with polish.
I will continue to post any progress here and post links to future projects.

More Software work

I think I have the beginnings of some reasonable demo code well on the way.  Currently, it implements writing immediate values to registers, copying registers, using flow control operations to generate delays and call subroutines.  It performs mathematical operations like multiplication, addition and subtraction, logical operations like shift-right logical, xor and "and" operations, and conditional loops, jump-returns and breaks within 293 lines of machine code.

That's right, with a custom array of op-codes, I cannot program in high-level or even assembly language.  I have to write out each instruction as a 64-bit hexadecimal value.  In first year they tell you, "Don't worry, you will never have to even look at machine language.  The worst you will see is inline assembly."

<edit> Here is a link to a video of the work in progress.  There's no audio except the clicking of the switches.

Hardware Complete(-ish); Software on its Way!

It seems that, if I wish to implement a division operator, I will have to generate a whole new component to take care of it.  Quartus will not synthesize a division operator with STD_LOGIC_UNSIGNED elements.  So that may have to be held over for recreational programming time.  Otherwise, my program control operators are working beautifully and my biggest problem has been missing details in my memory initialization file.  But who ever said programming in machine language was fun?  I feel confident that my design meets or exceeds my expectations at this point.  All that remains is the demo and the final report.  As far as I'm concerned, this project already falls under the SUCCESS column.  I'll post a video soon of the working board.

More good news

Things are swimming along now.  I have successfully tested about 60% of my operation codes with mostly positive results.  Some of my program control ops are having difficulty: notably, JMP and RET.  I would have liked to have those working by now.  I have successfully managed to display a scrolling marquee on the 7-segment HEX components and displayed the state of the switches on the red LEDs.  Now I am working on incrementing the value of the green LEDs with a delay generated by a JMP to a subroutine and a RET to the next stage, but it keeps jumping to the very beginning of the program.  It will take some time to set it up in ModelSim so I've been flashing the board about as frequently as compile-time will allow.  It's late and my brain hurts.  More work for another day.

Software Progress

After some hard work this morning, a preliminary demo program is about 1/3 done.  I'm currently compiling for test right now, which takes about 2.5 minutes on this PC and 5 minutes on my laptop...
more hardware work clearly needs doing but things are looking up!

GREAT SUCCESS!!!!!!!!!

Everything seems to be working much better now.  Of course, I currently have my DE1 counting back from 4,294,967,295 to 0, which may take a bit longer than I want, but we'll see what happens.  Anyway, the registers are taking the right values and the I/O seems to be displaying correctly.  Much testing and machine code is yet to come.  Stay tuned.  Next comes writing the software.

Problems with memory

Having used the Quartus megafunction wizard to implement my program ROM seems to be causing a great deal of problems at this point in the design phase.  When testing all other aspects of my design in ModelSim, they operate effectively and predictably, but when I re-integrate the memory and flash my DE-1 board, the results become unpredictable.  I can see that values are repeatedly being written to the registers my program calls, but the values are far from predictable.  Since the ROM and its memory initialization file can't be simulated properly by ModelSim, it's next to impossible to pinpoint the source of the data loss.  I have attempted to create a combinational "memory" but that has also had no results thus far.  Can't keep working all night.  Need rest.  More to come...

More Encouraging Results

After another day of grinding away, things are looking good.  On the hardware side, all that remains - barring further disaster - is completing the state machine and on-board testing.  Then I can begin designing some demo code.  If that all goes fast enough, I may have time to start an ASM compiler.  That, and pass my other courses, that is! I now feel like I'm where I should be with the project, so the pressure is off.

Disaster Recovery

After discovering on friday that something ugly was occurring somewhere between my memory unit and my registers, I was forced to - essentially - disassemble my design and put it back together, element by element.  The biggest problem was that I couldn't run my tests in modelSim with the memory properly initialized so I couldn't see where my data was getting scrambled.  After the better part of a day working on it, and basically rewriting 80% of it, I'm able to test, and am getting some promising results.  The control unit is still far from complete, but the values I enter are going into the registers I call.  This is a good sign, even though this was, for all intents and purposes, where I thought I was last week.

Tangible results

Yesterday, I resolved some major issues with some help and direction from Steve.  I took a stab in the dark and flashed my board, and lo and behold, the hex and leds began flashing at random. Considering how sparse my state machine is, that's exactly what I was expecting. A good four hours of solid hdl work and some preliminary coding and let the testing begin!

Frustrations

I am running into many snags now, with the alu and control module. It's slowing me down but I'm certain I can get it up and running in no time. Also, the deadline for the progress report is fast approaching so it's time for my least favorite task.

Operation control

After consulting with Steve, I have some great momentum again.  Some of the more technical aspects of VHDL and digital logic are coming back to me and the structure of my descriptions are becoming more precise.  I am almost ready to start describing the state machine that drives the ALU and register access.  I am implementing a modified and abridged version of the MIPS operation set. So far, I have selected 34 basic operations that I would like to implement, and will try to get the mathematical ones up and running by week's end.  The program operations - break, jump, etc. - will be next, and then we'll see about the memory access ones, like load word and such.  I have enough registers at the moment that I needn't worry about write memory functions for the time being.

More to come soon.

I/O Registers

After some trial and error, I have the I/O register hardware simulating nicely in ModelSim.  Still struggling with memory and the ALU's state machine at this point but things are coming along.  Once I meet with Steve the rest of the hardware should be easy enough.  Then it's on to platform testing.  Time to dust off the ol' DE1 again!

Software registers

<p>Preliminary tests on the sw regs are promising. 64 of them ought to be <br>
plenty. Still reasoning out how to use an sfr to control the gpios but lots of time for that.

The Beginning

This post marks the beginning of my EECE 496 project: MicorProcessor5.

I have met  with my technical supervisor, and signed up through vista.  I have mostly completed my project proposal memo and am currently working on the Gantt chart for the timeline.  I have also begun some preliminary signal description for the outer layers of the MP.  I couldn't help myself.  More to come...