A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Saturday, July 14, 2012
More good news
Things are swimming along now. I have successfully tested about 60% of my operation codes with mostly positive results. Some of my program control ops are having difficulty: notably, JMP and RET. I would have liked to have those working by now. I have successfully managed to display a scrolling marquee on the 7-segment HEX components and displayed the state of the switches on the red LEDs. Now I am working on incrementing the value of the green LEDs with a delay generated by a JMP to a subroutine and a RET to the next stage, but it keeps jumping to the very beginning of the program. It will take some time to set it up in ModelSim so I've been flashing the board about as frequently as compile-time will allow. It's late and my brain hurts. More work for another day.
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