A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Thursday, July 12, 2012
Problems with memory
Having used the Quartus megafunction wizard to implement my program ROM seems to be causing a great deal of problems at this point in the design phase. When testing all other aspects of my design in ModelSim, they operate effectively and predictably, but when I re-integrate the memory and flash my DE-1 board, the results become unpredictable. I can see that values are repeatedly being written to the registers my program calls, but the values are far from predictable. Since the ROM and its memory initialization file can't be simulated properly by ModelSim, it's next to impossible to pinpoint the source of the data loss. I have attempted to create a combinational "memory" but that has also had no results thus far. Can't keep working all night. Need rest. More to come...
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