A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Sunday, July 15, 2012
Hardware Complete(-ish); Software on its Way!
It seems that, if I wish to implement a division operator, I will have to generate a whole new component to take care of it. Quartus will not synthesize a division operator with STD_LOGIC_UNSIGNED elements. So that may have to be held over for recreational programming time. Otherwise, my program control operators are working beautifully and my biggest problem has been missing details in my memory initialization file. But who ever said programming in machine language was fun? I feel confident that my design meets or exceeds my expectations at this point. All that remains is the demo and the final report. As far as I'm concerned, this project already falls under the SUCCESS column. I'll post a video soon of the working board.
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