A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Monday, July 2, 2012
More Encouraging Results
After another day of grinding away, things are looking good. On the hardware side, all that remains - barring further disaster - is completing the state machine and on-board testing. Then I can begin designing some demo code. If that all goes fast enough, I may have time to start an ASM compiler. That, and pass my other courses, that is! I now feel like I'm where I should be with the project, so the pressure is off.
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