A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Friday, July 13, 2012
GREAT SUCCESS!!!!!!!!!
Everything seems to be working much better now. Of course, I currently have my DE1 counting back from 4,294,967,295 to 0, which may take a bit longer than I want, but we'll see what happens. Anyway, the registers are taking the right values and the I/O seems to be displaying correctly. Much testing and machine code is yet to come. Stay tuned. Next comes writing the software.
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