A VHDL project with the goal of generating a microcontroller for the Altera DE-1 board. This is for my 2012 UBC EECE 496 project, but will most likely be ongoing well after the course is complete.
Sunday, July 1, 2012
Disaster Recovery
After discovering on friday that something ugly was occurring somewhere between my memory unit and my registers, I was forced to - essentially - disassemble my design and put it back together, element by element. The biggest problem was that I couldn't run my tests in modelSim with the memory properly initialized so I couldn't see where my data was getting scrambled. After the better part of a day working on it, and basically rewriting 80% of it, I'm able to test, and am getting some promising results. The control unit is still far from complete, but the values I enter are going into the registers I call. This is a good sign, even though this was, for all intents and purposes, where I thought I was last week.
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